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ISL97644
Data Sheet December 14, 2007 FN9228.1
Boost + LDO + VON Slice + VCOM
The ISL97644 represents an integrated DC/DC regulator for monitor and notebook applications with screen sizes up to 20". The device integrates a boost converter for generating AVDD, a VON slice circuit, an integrated logic LDO and a high performance VCOM amplifier. The boost converter features a 2.6A FET and has user programmable soft-start and compensation. With efficiencies up to 92%, the AVDD is user selectable from 7V to 20V. The logic LDO includes a 350mA FET for driving the low voltage needed by the external digital circuitry. The VON slice circuit can control gate voltages up to 30V. High and low levels are programmable, as well as discharge rate and timing. The integrated VCOM features high speed and drive capability. With 30MHz bandwidth and 50V/s slew rate, the VCOM amplifier is capable of driving 400mA peaks, and 100mA continuous output current.
Features
* 3V to 5.5V Input * 2.6A Integrated Boost for Up to 20V AVDD * Integrated VON Slice * 350mA VLOGIC LDO - 2.5V, 2.85V, 3.3V Output Voltage Selectable * 600kHz/1.2MHz fS * VCOM Amplifier - 30MHz BW - 50V/s SR - 400mA Peak Output Current * UV and OT Protection * 24 Ld 4x4 QFN * Pb-Free (RoHS Compliant)
Applications
* LCD Monitors (15"+) * Notebook Display (up to 16")
Pinout
ISL97644 (24 LD 4x4 QFN) TOP VIEW
ENABLE PGND
Ordering Information
TEMP. RANGE PART NUMBER PART (C) (Note) MARKING ISL97644IRZ
18 17 16 15 14 13 LX VIN_2 FREQ COMP SS VIN_1
VGH
RE
CE
24 GND VGH_M VFLK VDPM VDD_1 VDD_2 1 2 3 4 5 6 7 OUT
23
22
21
20
FB
PACKAGE (Pb-Free)
PKG. DWG. #
19
97644IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D 97644IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D Tape & Reel
ISL97644IRZ-T*
ISL97644IRZ-TK* 97644IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D Tape & Reel *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
8 NEG
9 POS
10 AGND
11 ADJ
12 LDO_OUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97644 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME GND VGH_M VFLK VDPM VDD_1 VDD_2 OUT NEG POS AGND ADJ LDO_OUT VIN_1 SS COMP FREQ VIN_2 LX ENABLE FB PGND CE RE VGH Ground Gate Pulse Modulation Output Gate Pulse Modulation Control Input Gate Pulse Modulation Enable Gate Pulse Modulation Lower Voltage Input VCOM Amplifier Supply VCOM Amplifier Output VCOM Amplifier Inverting Input VCOM Amplifier Noninverting Input VCOM Amplifier Ground LDO Output Adjust Pin LDO Output LDO power supply Boost Converter Soft-start. Connect a capacitor between this pin and GND to set the soft-start time. Boost Converter Compensation Pin. Connect a series resistor and capacitor between this pin and GND to optimize transient response. Boost Converter Frequency Select. Boost Converter Power Supply Boost Converter Switching Node Chip Enable Pin. Connect to VIN1 for normal operation, GND for shutdown. Boost Converter Feedback Boost Converter Power Ground Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time. Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate. Gate Pulse Modulator High Voltage Input FUNCTION
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ISL97644
Absolute Maximum Ratings
Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V VDD2, OUT, NEG and POS to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . . -0.5 to +25V VDD1, VGH and VGH_M to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . . -0.5 to +32V Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . 6V Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . 0.5V All Other Pins to GND, AGND and PGND . . . . . . . . . . -0.5 to +6.5V Input, Output, or I/O Voltage . . . . . . . . . . . GND -0.3V to VIN + 0.3V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) 4x4 QFN Package (Notes 1, 2) . . . . . . 39 2.5 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Continuous Junction Temperature . . . . . . . . . . . +125C Power Dissipation TA +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W TA = +70C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W TA = +85C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W TA = +100C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . 8V to 20V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22F Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H LDO Output Capacitance. . . . . . . . . . . . . . . . . . . . . . .2.2F to 10F Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 2x22F Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
SYMBOL GENERAL VS IS_DIS IS UVLO
VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40C to +85C Unless Otherwise Noted. TEST CONDITION MIN TYP MAX UNIT
PARAMETER
VIN1, VIN2 Input Voltage Range Sum of VIN1, VIN2 Supply Currents when Disabled Sum of VIN1, VIN2 Supply Currents Undervoltage Lockout Threshold
See separate LDO specifications ENABLE = 0V ENABLE = 5V, LX not switching, LDO not loaded VIN2 Rising VIN2 Falling
3.0
5.0 0.2 1
5.5 2
V A mA
2.3 2.2
2.45 2.35 140 100
2.6 2.5
V V C C
OTR OTF
Thermal Shutdown Temperature
Temperature Rising Temperature Falling
LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM VIL VIH RIL Low Voltage Threshold High Voltage Threshold Pull-Down Resistor Enabled, Input at VIN2 2.2 150 250 400 0.8 V V k
STEP-UP SWITCHING REGULATOR AVDD AVDD/IOUT AVDD/VIN ACCAVDD Output Voltage Range Load Regulation Line Regulation Overall Accuracy (Line, Load, Temperature) 50mA < ILOAD < 250mA ILOAD = 150mA, 3.0 < VIN1 < 5.5V 10mA < ILOAD < 300mA, 3.0 < VIN1 < 5.5V, 0C < TA < +85C -3 VIN*1.25 0.2 0.15 0.25 3 20 V % %/V %
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ISL97644
Electrical Specifications
SYMBOL VFB VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40C to +85C Unless Otherwise Noted. (Continued) TEST CONDITION ILOAD = 100mA, TA = +25C ILOAD = 100mA, TA = -40C to +85C IFB RDS(ON) EFF ILIM DMAX FOSC FB Input Bias Current Switch On Resistance Peak Efficiency Switch Current Limit Max Duty Cycle Oscillator Frequency FREQ = 0V FREQ = VIN2 ISS Soft-Start Slew Current SS < 1V, TA = +25C 2.1 85 550 1.0 MIN 1.20 1.19 TYP 1.21 1.21 250 150 92 2.6 90 650 1.2 2.75 800 1.4 MAX 1.22 1.23 500 300 UNIT V V nA m % A % kHz MHz A
PARAMETER Feedback Voltage (VFB)
LDO REGULATOR VSL Input Voltage Range VIN1 ADJ = LDO_OUT ADJ OPEN ADJ = 0V VLDO Output Voltage ADJ = GND, ILDO = 1mA ADJ = GND, ILDO = 350mA ADJ OPEN, ILDO = 1mA ADJ OPEN, ILDO = 350mA ADJ = LDO_OUT, ILDO = 1mA ADJ = LDO_OUT, ILDO = 350mA ACCLDO VLDO/VIN VLDO/IOUT VDO ILIML Overall Accuracy Line Regulation Load Regulation Dropout Voltage Current Limit 1mA < ILDO < 350mA ILDO = 1mA, 3.0V < VIN1 < 5.5V 1mA < ILDO < 350mA Output drops by 2%, ILDO = 350mA Output drops by 2% 350 -4 2 0.75 300 400 500 3.0 3.35 3.8 3.31 3.29 2.86 2.84 2.51 2.49 4 5.5 5.5 5.5 V V V V V V V V V % mV/V % mV mA
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated VSAMP ISAMP VOS IB CMIR CMRR PSRR VOH VOH VOL VOL Supply Voltage Supply Current Offset Voltage Noninverting Input Bias Current Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing High Output Voltage Swing High Output Voltage Swing Low Output Voltage Swing Low Iout(source) = 5mA Iout(source) = 50mA Iout(sink) = 5mA Iout(sink) = 50mA 0 50 70 70 85 VDD2 - 50 VDD2 - 450 50 450 4.5 3 3 0 20 100 VDD2 20 V mA mV nA V dB dB mV mV mV mV
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ISL97644
Electrical Specifications
SYMBOL ISC SR BW VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40C to +85C Unless Otherwise Noted. (Continued) TEST CONDITION MIN 250 TYP 400 50 -3dB gain point 30 MAX UNIT mA V/s MHz
PARAMETER Output Short Circuit Current Slew Rate Gain Bandwidth
GATE PULSE MODULATOR VGH IVGH VGH Voltage VGH Input Current VFLK = 0 RE = 33k, VFLK = VDD1 VDD1 IVDD1 RONVGH IDIS_VGH TDEL NOTES: 1. Nominal discharge current = 300/(RE+5k). 2. Nominal delay time = 4000*CE. VDD1 Voltage VDD1 Input Current VGH to VGH_M On Resistance VGH_M Discharge Current (Note 1) RE = 33k DELAY Time (Note 2) CE = 470pF, RE = 33k 3 -2 0.1 70 8 1.9 7 260 40 VGH - 2 2 30 V A A V A mA s
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I
Typical Performance Curves
100 90 LOAD REGULATION (%) 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 200 400 600 800 IAVDD (mA) 1000 1200 FOSC = 1.2MHz FOSC = 650kHz 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 0 200 400 600 800 IAVDD (mA) 1000 1200 FOSC = 1.2MHz FOSC = 650kHz
FIGURE 1. AVDD EFFICIENCY vs IAVDD
FIGURE 2. AVDD LOAD REGULATION vs IAVDD
10.5
L = 10H, COUT = 40F, CCOMP = 2.2nF, RCOMP = 10k
10.45 AVDD 150mA 10.4 AVDD (V) 10.35 10.3 10.25 10.2 10.15 3 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 AVDD (AC COUPLED) AVDD 500mA IAVDD
FIGURE 3. LINE REGULATION AVDD vs VIN
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
3.4 LDO LOAD REGULATION (%) 3.3 3.2 3.1 LDO_OUT (V) 3.0 2.9 2.8 2.7 2.6 2.5 2.4 3 2.5V OUTPUT, 100mA 4 VIN (V) 2.5V OUTPUT, 350mA 2.85V OUTPUT, 100mA 2.85V OUTPUT, 350mA 3.3V OUTPUT, 100mA 3.3V OUTPUT, 350mA
0 -0.2 -0.4 -0.6 ADJ = OPEN -0.8 -1.0 -1.2 5 6 ADJ = 0
ADJ = LDO_OUT
0
100
200 IO (mA)
300
400
FIGURE 5. LINE REGULATION LDO_OUT vs VIN
FIGURE 6. LDO LOAD REGULATION vs IO
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ISL97644 Typical Performance Curves (Continued)
CE = 1pF, RE = 100k CE = 1000pF, RE = 100k
VGH_M
VGH_M
VFLK
VFLK
FIGURE 7. GPM CIRCUIT WAVEFORM
FIGURE 8. GPM CIRCUIT WAVEFORM
CE = 10pF, RE = 100k
CE = 10pF, RE = 150k
VGH_M
VGH_M
VFLK
VFLK
FIGURE 9. GPM CIRCUIT WAVEFORM
FIGURE 10. GPM CIRCUIT WAVEFORM
INPUT SIGNAL INPUT SIGNAL
OUTPUT SIGNAL
OUTPUT SIGNAL (-3dB ATTENTUATION FROM INPUT SIGNAL)
FIGURE 11. VCOM RISING SLEW RATE
FIGURE 12. VCOM BANDWIDTH MEASUREMENT
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FN9228.1 December 14, 2007
ISL97644 Block Diagram
FREQ LX
OSCILLATION GENERATOR SLOPE COMPENSATION COMP FB + SUMMING AMPLIFIER PWM LOGIC
+
2.5A PGND
SS VIN2 VDPM
REFERENCE GENERATOR
START-UP AND FAULT CONTROL
ENABLE
LDO CONTROLLER
ADJ
VIN1
LDO_OUT VDD2
OUT
+ -
POS NEG GND
GPM CIRCUIT
VDD1
VFLK
VGH VGH_M CE
RE
FIGURE 13. ISL97644 BLOCK DIAGRAM
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FN9228.1 December 14, 2007
ISL97644 Typical Application Diagram
VIN VIN2 C1 22F C3 2.2nF L1 10H D1 AVDD R1 10k C9 (OPTIONAL) COMP BOOST FB PGND R2 1.3k
LX
C2 47F
R5 C4 10k 10nF SS
ENABLE
FREQVGH VDPM VFLK C5 470P CE RE R6 130k AVDD R7 80k VCOM +4.0V C6 0.1F R3 2k POS GPM CIRCUIT VGH_M VDD2 C10 2.2F VDD_1
VON
TO ROW DRIVER
C11 1F NEGOUT VIN1 LDO_OUT AGND LDO GND CONTROLLER ADJ C7 4.7F VLOGIC
FIGURE 14. TYPICAL APPLICATION DIAGRAM
Applications Information
The ISL97644 provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate AVDD voltage for column drivers, one logic LDO regulator to provide voltage to logic circuit in the LCD panel, one integrated VCOM buffer which can provide up to 400mA peak current. This part also integrates Gate Pulse Modulator circuit that can help to optimize the picture quality.
Boost Converter
Frequency Selection
The ISL97644 switching frequency can be user selected to operate at either constant 650kHz or 1.2MHz. Lower switching frequency can save power dissipation, while higher switching frequency can allow smaller external components like inductor and output capacitors, etc. Connecting FREQ pin to ground sets the PWM switching frequency to 650MHz, or connecting FREQ pin to VIN for 1.2MHz.
Enable Control
When enable pin is pulling down, the ISL97644 is shut down reducing the supply current to <10A. When the voltage at enable pin reaches 2.2V, the ISL97644 is on.
Soft-Start
The soft-start is provided by an internal 2.5A current source to charge the external soft start capacitor. The ISL97644 ramps up current limit from 0A up to full value, as the voltage at SS pin ramps from 0 to 1.2V. Hence the soft-start time is 4.8ms when the soft-start capacitor is 10nF, 22.6ms for 47nF and 48ms for 100nF.
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Operation
The boost converter is a current mode PWM converter operating at either a 650kHz or 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by:
V Boost 1 ------------------ = -----------1-D V IN
The current through the MOSFET is limited to 2.6APEAK. This restricts the maximum output current (average) based on the following equation:
I L V IN I OMAX = I LMT - -------- x -------- 2 VO
(EQ. 3)
Where IL is peak to peak inductor ripple current, and is set by:
V IN D I L = --------- x --L fs
(EQ. 1)
(EQ. 4)
Where D is the duty cycle of the switching MOSFET. Figure 13 shows the block diagram of the boost regulator. It uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by the following equation:
R1 + R2 V Boost = -------------------- x V FB R2
where fS is the switching frequency (650kHz or 1.2MHz). The Table 2 gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX).
Capacitor
An input capacitor is used to suppress the voltage ripple injected into the boost converter. The ceramic capacitor with capacitance larger than 10F is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 1 for input capacitor.
TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/16V 10F/10V SIZE 1206 0805 1210 MFG TDK Murata Murata PART NUMBER C3216X7R1C106M GRM21BR61A106K GRB32ER61A226K
(EQ. 2)
22F/10V
TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) 3 3 3 5 5 5 5 3 3 3 5 5 5 5 VO (V) 9 12 15 9 12 15 18 9 12 15 9 12 15 18 L (H) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Fs (MHz) 0.65 0.65 0.65 0.65 0.65 0.65 0.65 1.2 1.2 1.2 1.2 1.2 1.2 1.2 IOMAX (mA) 636 419 289 1060 699 482 338 742 525 395 1236 875 658 514
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Inductor
The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3H to 10H are used to match the internal slope compensation. The inductor must be able to handle the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2 (EQ. 5)
capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. COUT in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. The following table shows some selections of output capacitors.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE 1210 1210 MFG TDK Murata PART NUMBER C3225X7R1E106M GRM32DR61E106K
Some inductors are recommended in Table 3.
TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR 6.8H/3APEAK 10H/4APEAK DIMENSIONS (mm) 7.3x6.8x3.2 8.3X8.3X4.5 MFG TDK Sumida PART NUMBER RLF7030T-6R8N3R0 CDR8D43-100NC
10F/25V 10F/25V
Compensation
The boost converter of ISL97644 can be compensated by a RC network connected from CM1 pin to ground. 4.7nF and 10k RC network is used in the demo board. The larger value resistor and lower value capacitor can lower the transient overshoot, however, at the expense of stability of the loop.
5.2H/4.55APEAK 10x10.1x3.8
Cooper CD1-5R2 Bussmann
Rectifier Diode
A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table is some recommendations for boost converter diode.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE SS23 MBRS340 SL23 VR/IAVG RATING 30V/2A 40V/3A 30V/2A PACKAGE SMB SMC SMB MFG Fairchild Semiconductor International Rectifier Vishay Semiconductor
Cascaded MOSFET Application
An 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed as shown in Figure 15. The voltage rating of the external MOSFET should be greater than AVDD.
VIN AVDD
LX FB Intersil ISL97644
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x --C OUT f s VO (EQ. 6) FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS
Linear-Regulator (LDO)
The ISL97644 includes a LDO with adjustable output, and it can supply current up to 350mA. The output voltage is adjusted by connection of ADJ pin. When ADJ pin is connected to ground, the output voltage is set to 3.3V; when ADJ pin is floating, the output voltage is set to 2.85V, and when ADJ pin is connected to LDO_OUT pin, the output voltage is set to 2.5V.
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output
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The efficiency of LDO is depended on the difference between input voltage and output voltage, as well as the output current:
( % ) = ( V IN1 - V LDO_OUT ) x I LDO_OUT x 100% (EQ. 7)
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way multiplexer, switching VGHM between ground, VDD1 and VGH. Voltage selection is provided by digital inputs VDPM (enable) and VFLK (control). High to low delay and slew control is provided by external components on pins CE and RE, respectively. A block diagram of the gate pulse modulator circuit is shown in Figure 16. When VDPM is LOW, the block is disabled and VGHM is grounded. When VDPM is HIGH, the output is determined by VFLK. When VFLK goes high, VGHM is pulled to VGH by a 70 switch. When VFLK goes low, there is a delay controlled by capacitor CE, following which VGHM is driven to VDD1, with a slew rate controlled by resistor RE. Note that VDD1 is used only as a reference voltage for an amplifier, thus does not have to source or sink a significant DC current.
The less difference between input and output voltage, the higher efficiency it is. The minimum dropout voltage of LDO of ISL97644 is 300mV. The ceramic capacitors are recommended for the LDO input and output capacitor. Larger capacitors help reduce noise and deviation during transient load change.
VGH
VGH_M EnGPM1
+
VDD1
-
x240
+
VREF
RE 200A
CE FN9228.1 December 14, 2007
VFLK
CONTROL AND TIMING
FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
12
+
ISL97644
Low to high transition is determined primarily by the switch resistance and the external capacitive load. High to low transition is more complex. Take the case where the block is already enabled (VDPM is H). When VFLK is H, pin CE is grounded. On the falling edge of VFLK, a current is passed into pin CE, to charge an external capacitor to 1.2V. This creates a delay, equal to CE*4200. At this point, the output begins to pull down from VGH to VDD1. The slew current is equal to 300/(RE+5000)*Load Capacitance. and inductor to disconnect the DC path when the part is disabled.
TO INDUCTOR INPUT
ENABLE
VDPM 0
FIGURE 19. CIRCUIT TO DISCONNECT THE DC PATH OF BOOST CONVERTER
VFLK 0 SLOPE CONTROLLED BY RE AND LOAD CAPACITANCE VGH VGH_M VDD_1 0 DELAY TIME CONTROLLED BY CE
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back plate of an LCD display. This plate is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rate for the display. Thus the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100mA for typical applications). The ISL97644 VCOM amplifier's output current is limited to 400mA. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen on the s time scale in practical systems and for pulses 2 or 3 times the current limit, the VCOM voltage will have settled again before the next line is processed.
FIGURE 17. GATE PULSE MODULATOR TIMING DIAGRAM
Start-Up Sequence
Figure 18 shows a detailed start up sequence waveform.
VIN 0
ENABLE 0
VIN THRESHOLD
VDPM
0
Fault Protection
ISL97644 provides the overall fault protections including over current protection and over-temperature protection.
AVDD LDO OUTPUT VGH_M
0
FIGURE 18. START-UP SEQUENCE
An internal temperature sensor continuously monitors the die temperature. In the event that die temperature exceeds the thermal trip point, the device will shut down and disable itself. The upper and lower trip points are typically set to +140C and +100C respectively.
When VIN exceeds 2.5V and ENABLE reaches the VIH threshold value, Boost converter and LDO start up, and gate pulse modulator circuit output holds until VDPM goes to high. Note that there is a DC path in the boost converter from the input to the output through the inductor and diode, hence the input voltage will be seen at output with a forward voltage drop of diode before the part is enabled. If this voltage is not desired, the following circuit can be inserted between input
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FN9228.1 December 14, 2007
ISL97644 Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VIN and VDD bypass capacitors close to the pins. 3. Reduce the loop area with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for control circuit. 9. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN9228.1 December 14, 2007
ISL97644
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06
4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25)
PIN 1 INDEX AREA
18
1
4.00
2 . 50 0 . 15
13
(4X)
0.15 12 7 0.10 M C A B 0 . 07 24X 0 . 23 + 0 . 05 4 24X 0 . 4 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0 . 1
( 3 . 8 TYP )
C BASE PLANE
SIDE VIEW
SEATING PLANE 0.08 C
(
2 . 50 ) ( 20X 0 . 5 )
C ( 24X 0 . 25 ) ( 24X 0 . 6 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
15
FN9228.1 December 14, 2007

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